Alatek $100K Breaks Price Barrier - 3 Million ASIC gate Emulator
EDA Editors and Technical Editors
Las Vegas, NV-- (BUSINESS WIRE)—September 16, 2002—Alatek, Inc. introduces a new 3 million ASIC gate design emulator at $99,600 “Permanent License Purchase”, which is a fraction of what other EDA vendors require for similar capacity and performance products. The product, COMULATOR™ 3M, is based on a new release of Alatek's proprietary (HES™3.0) hardware embedded simulation technology.
“Lab teams who thought they could not afford emulation will find no extreme prices here. Until now, it has been impossible to purchase high-performing emulation products for an affordable price. Breaking the $100K price barrier brings emulation into the mainstream and making COMULATOR-3M the most popular and flexible design verification tool, for the majority of today's designs” - said Lori Swenson, Director of Strategic Marketing at Alatek.
COMULATOR-3M is not a large 300lb. external chassis, rather a compact unique form-factor, which enables all hardware to reside with the HDL simulation workstation and can support a maximum capacity up to 15 Million ASIC gates. Alatek hardware features on-board clock speeds of 20-33 MHz. To best fulfill the customer needs, Alatek hardware is delivered on “off-the-shelf” SUN® workstations, entry-level servers, and high performance PC platforms. COMULATOR-3M is working under UNIX, LINUX and NT/XP operating systems, and may be transferred between platforms at any time. The COMULATOR-3M emulator product fits within the main ASIC prototyping and FPGA design flows and uses customer's existing HDL simulation and synthesis tools. This minimizes costs, cuts learning curve and lowers the risk involved in bringing a new design verification technology. Popular HDL simulators such as, Synopsys®, Cadence®, Mentor® and Aldec® are supported, via PLI and VHPI interfaces and this includes VHDL, Verilog and mixed language versions.
Since COMULATOR-3M is a network-based product, designs or design section can be prepared off-line and then processed on network servers. This allows companies to prioritize verification of various design sections and systems and maximizes benefits of the investment. Using the same verification tools and process for the entire company is improving design quality and is speeding product release cycle.
“For less than $100K designers will be able to expedite even the most intricate 3 million ASIC gate designs, particularly that COMULATOR-3M doubles as hardware accelerator and system prototyping environment,” stated Ms. Swenson.
COMULATOR-3M installation takes only one to two days and first design preparation for emulation may take additional days. Generally, designers can start emulation, design acceleration and incremental ASIC design prototyping within one week of product delivery. The follow-on designs are rudimentary once the memory modeling and clocking have been resolved. Alatek also provides basic courses on emulation technology, hardware acceleration and incremental ASIC prototyping. These courses are conducted at Alatek headquarters in Las Vegas, Nevada.
Pricing and Availability
The COMULATOR-3M emulator is available now at $99,600 US DOLLARS “Permanent License” Purchase. Price includes COMULATOR hardware and Alatek proprietary DVM, Design Verification Manager application. Price does not include on-site installation/training fees, additional EMA board(s), or cost of the “off-the-shelf” workstation(s). Customers may choose workstation system configurations prior to shipment from factory or on-site installation. Advanced on-board clock hardware (20-33MHz) available on or before November 2002. For more information, visit www.alatek.com for sales locations.
About Alatek
Alatek, Inc. incorporated in 1996 is headquartered in Nevada. Alatek is a privately owned with four corporate offices and research centers in the United States and Europe. Alatek offers innovative design verification solutions, which are complimentary add-ons to the customers' existing design environments and EDA tools. Alatek specializes in the development of Hardware/Software co-design tools, hardware accelerators, intellectual property (IP) cores and other technologies. Having broad expertise in design simulation and verification, particularly for Altera® and Xilinx® FPGA/CPLD devices, Alatek operates as a full-service design house. Corporate headquarters are located at 3753 Howard Hughes Pkwy, Suite 200-2018, Las Vegas, NV 89109. For additional information, visit Alatek corporate website at www.alatek.com.
